Сайт пошуку роботи №1 в Україні
Вакансія від 21 травня 2024
Intern Digital Engineer (Fixed-Term Contract)
IT; 50–250 співробітників-
Львів, вулиця Кам'янецька, 33.
3,4 км від центру - Повна зайнятість. Також готові взяти студента.
- Verilog/VHDL
- SystemC/Verilog
- TCL
- Python
- Bash
- Perl
- C/C++
- HW
- FPGA design workflow
- digital circuits
- Simulation
- verification
- UART
- I2C
- SPI
- JTAG
- RTL logic design
- PCB design
- FPGA
- Microcontrollers
- Arduino
Опис вакансії
Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.
For more information, visit https://www.renesas.com
The Role:
- Design of basic digital circuits meeting performance and area.
- Simulation, verification, and lab evaluation of digital circuits.
- Demonstrates an ability to learn new tool features and procedures.
- Attend training courses.
- Build up your knowledge and improve your skills using your own research.
What we are looking for:
- University students at Electrical Engineering, Computer Engineering, Computer Science or related disciplines.
- Preferably university experience in design of digital circuits.
- Knowledge of electrical properties, digital circuits, behavioral modeling and simulation and Unix.
- Understanding of HW or FPGA design workflow.
- Ability to prioritize work, set goals and meet deadlines.
- Self-motivated and take full responsibility for solutions.
- Good written, communication and teamwork skills.
- Pre-Intermediate English level.
Will be a plus:
- Knowledge of transistor-level integrated circuits and semiconductor physics.
- Experience with protocols (UART, I2C, SPI, JTAG, etc.).
- Knowledge of PCB design, FPGA, Microcontrollers, Arduino.
- Programming/scripting (Verilog/VHDL, SystemC/Verilog, TCL, Python, Bash, Perl, C/C++).
- Familiarity with RTL logic design, design constraints, synthesis, P&R, static timing analysis and formal verification.
- Understanding of advanced verification methodologies (e.g. UVM, ABV).
We offer
- Fixed-Term Contract — duration approx. 6 months.
- Friendly and highly professional team.
- 14 calendar days paid vacation.
- Flexible working hours.
- Professional & personal growth.
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